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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1

User’s Manual U15905EJ2V1UD

215

The conditions when the TMn register becomes 0000H are shown below.

(a) Asynchronous reset

TMCAEn bit of TMCn0 register = 0

After reset

(b) Synchronous reset

TMCEn bit of TMCn0 register = 0

The CCn0 register is used as a compare register, and the TMn and CCn0 registers match when clearing

the TMn register is enabled (CCLRn bit of the TMCn1 register = 1)

(2) Capture/compare registers n0 and n1 (CCn0 and CCn1) (n = 0, 1)

These capture/compare registers (n0 and n1) are 16-bit registers.

They can be used as capture registers or compare registers according to the CMSn0 and CMSn1 bit

specifications of timer mode control register n1 (TMCn1) (n = 0, 1).

These registers can be read or written in 16-bit units. (However, write operations can only be performed in

compare mode.)

These registers are cleared to 0000H after reset.

CC1n

CC0n

FFFFF602H,

FFFFF604H

FFFFF612H,

FFFFF614H

0000H

Address

After reset

Remark

n = 0, 1

(a) Setting these registers as capture registers (CMSn0 and CMSn1 of TMCn1 = 0)

When these registers are set as capture registers, the valid edges of the corresponding external interrupt

signals INTPn0 and INTPn1 are detected as capture triggers. The timer TMn is synchronized with the

capture trigger, and the value of TMn is latched in the CCn0 and CCn1 registers (capture operation).

The valid edge of the INTPn0 pin is specified (rising, falling, or both rising and falling edges) according to

the IESn01 and IESn00 bits of the SESn register, and the valid edge of the INTPn1 pin is specified

according to the IESn11 and IESn10 bits of the SESn register (n = 0, 1).

The capture operation is performed asynchronously to the count clock. The latched value is held in the

capture register until another capture operation is performed (n = 0, 1).

When the TMCAEn bit of timer mode control register n0 (TMCn0) is 0, 0000H is read (n = 0, 1).

If these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of

signals INTPn0 and INTPn1 (n = 0, 1).

Caution

If the capture operation conflicts with the timing of disabling the TMn register from

counting (when the TMCEn bit of the TMCn0 register = 0), the captured data becomes

undefined. In addition, the INTCCn0 and INTCCn1 interrupts do not occur (n = 0, 1).

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